FIG. 1 shows a typical configuration for an integrated circuit including a flash EEPROM memory array 100 and circuitry enabling programming, erasing, reading, and overerase correction for memory cells in the array 100. The flash EEPROM array 100 is composed of individual cells, such as cell 102. Each cell has a drain connected to a bitline, such as bit line 104, each bitline being connected to a bitline switch circuit 106 and column decoder 108. Sources of the array cells are connected to each other and VSL, which is the common source signal, while their gates are each connected by a wordline to a row decoder 110.
The row decoder 110 receives voltage signals from a power supply 112 and distributes the particular voltage signals to the wordlines as controlled by a row address received from a processor or state machine 114. Likewise, the bitline switch circuit 106 receives voltage signals from the power supply 112 and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor 114. Voltages provided by the power supply 112 are provided as controlled by signals received from processor 114.
The column decoder 108 provides signals from particular bitlines to sense amplifiers or comparators 116 as controlled by a column address signal received from processor 114. The power supply 112 supplies voltages to column decoder 108 and bit lines 104. The sense amplifiers 116 further receive a signal from reference cells of reference array 118. With signals from the column decoder 108 and reference array 118, the sense amplifiers 116 then each provide a signal indicating a state of a bitline relative to a reference cell line to which it is connected through data latches or buffers 120 to processor 114.
To program a cell in the flash memory array 100, high gate-to-source voltage pulses are provided to the cell from power supply 112 while a source of the cell is grounded. For instance, during programming multiple gate voltage pulses typically of 10 V are each applied for approximately three to six microseconds to a cell, while a drain voltage of the cell is set to 4.5 V and its source is grounded. This 4.5 V bias from-drain to-source generates hot electrons near the drain side. The large gate-to-source voltage pulses enable a probability of hot electrons to overcome an energy barrier between the channel and floating gate formed by a thin dielectric layer, thereby driving hot electrons onto the floating gate of the cell. This programming procedure, termed “hot electron injection” results in an increase of a threshold voltage for the cell, the threshold being the gate-to-source voltage required for the cell to conduct.
To erase a cell in the flash memory array 100, a procedure known as Fowler-Nordheim tunneling is utilized wherein relatively high negative gate-to-source voltage pulses are applied for a few milliseconds each. For instance, during erase multiple gate voltage pulses of −10 V are applied to a cell, while a source of the cell is set to 5.5 V and its drain is floating. The large negative gate-to-source voltage pulses enable electrons to tunnel from the floating gate of a cell reducing its threshold.
In a flash memory array, all cells are typically erased simultaneously. Erasing of the memory cells is typically done by repeated applications of short erase pulses, described above, applied to each of the cells in the array, such as flash memory array 100. After each erase pulse, erase verify is performed cell by cell to determine if each cell in the array has a threshold above a limit, such as 3.0V, or if a cell is “undererased”. During execution of erase verify, current is measured to assure all cells have thresholds below the 3.0V limit required for an erased cell as described above. If an undererased cell is detected, an additional erase pulse is typically applied to the entire array. With such an erase procedure, a cell that is not undererased will also be repeatedly erased, and its control gate may eventually acquire a threshold below zero volts. A cell with a threshold erased below 0.5 volts, and sometimes 0 V, is referred to as being overerased.
Overerased cells have a threshold voltage that is too low and provide leakage current even when the gate-to-source voltage is at 0V. The cell leakage will form a non-negligible bit line current, which leads to reading and programming errors. Therefore, overerase correction is performed to reduce this bit line current. During overerase correction, all of the cells on a bit line in the flash memory array 100 have the same gate-to-source voltage with the source grounded. The drain voltage of the cell is set to around 5V. Again, hot electrons will be injected into the floating gate to raise the threshold voltages of the cells.
During programming, the bit line current of a bit line is composed of a cell current with the cell biased at programming condition and any cell currents provided by the unselected cells from the bit line. In general, the unselected cells have the gate-to-source voltage at ground level. During overerase correction, the bit line current is composed of all of the cell currents coming from all of the cells connected to the bit line. If overerase correction is done by bit line, all of the cells have equal gate-to-source voltages. If the overerase correction is done by a cell, the selected cell will have a different gate-to-source voltage from the other cells.
To represent a data bit, the floating gate of a cell is programmed or erased as described above. In a programmed state, the threshold voltage of a cell is typically set at greater than 5.0 volts, while the threshold voltage of a cell in an erased state is typically limited below 3.0 volts. To read a cell, a control gate voltage between 3.0 and 6.5 volts, typically 5 V, is applied. The 5 V read pulse is applied to the gate of an array cell as well as a cell in reference array 118 having a threshold near 3.5 V. In a programmed state with an array cell in array 100 having a threshold above 5.0 V, current provided by the reference cell with a threshold of 3.5 V will be greater indicating a programmed cell exists. In an erased state with a threshold of a cell in array 100 below 3.0 V, current provided by the array cell will be greater than the reference cell with a threshold of 3.5 V indicating an erased cell. To verify programming or erase, a read voltage is similarly applied to both a cell in the array and to cells in the reference array 118. For programming, a reference cell having a threshold of 5.0 V is used for a comparison, while for erase, a reference cell having a threshold of 3.0 V is used for comparison.
Overerased cells are undesirable because they create bit line leakage current during program or read procedures. For instance, during program or read, only one word line carries a positive voltage, while the remaining word lines are typically grounded. With word lines grounded, or at 0 V, a cell with a threshold voltage below about 0.5 V will conduct cell leakage current. A small leakage current in each cell will generate a non-negligible bit line leakage current since a bit line may have as many as, for example, 512 cells connected thereto. This leakage current will be enlarged one order of magnitude at high operating temperatures if the over-erased cell is operated in the sub-threshold region. With bit line leakage current, power supplies providing power to a bit line during programming may become overloaded. Similarly, with bit line leakage current during read, read errors may occur.
To prevent overerase, manufacturers of integrated circuits containing flash memory cells provide an overerase correction mechanism that typically seeks to “soft program” the overerased cells and raise their threshold voltages to a lower limit. Converging threshold voltages after erase prevents leakage current from overerased cells from causing read and program errors. U.S. Pat. No. 5,642,311 to Cleveland et al. provides a circuit for sensing overerased cells and applying programming pulses thereto that bring their threshold voltages back up to acceptable values. The circuit of Cleveland et al. uses ground level for the word line voltage and 5V on the bit line for overerase correction pulses. The approach of Cleveland et al. cannot provide sufficient bit line voltage as the bit line leakage current grows. FIG. 2 is a circuit schematic illustrating a single bit line 104, cell 102 and programming circuitry therefor. If power supply voltage VCC is lower than 5V, such as 3V or lower, charge pumping is required to pump the bit line voltage VBL above 3V during program and overerase correction. Charge pumps are typically utilized in low power devices, such as 3V devices currently utilized with battery powered notebook computers having flash memory arrays. The charged pumping capability must be large enough to sustain the bit line leakage current for efficient overerase correction. FIG. 2 illustrates the path of current I from PMOS QP0 passing through a bit line 104 to a cell 102 during overerase correction. VDQ1 is the output of the charge pumping circuit. If VCC is high enough, the charge pumping circuit is not needed. VDQ2 is the regulated voltage, which is the targeted bit line voltage during overerase correction. VR is the bandgap reference voltage provided to the differential amplifier 122, which regulates VDQ2 to VR*((Ra+Rb)/Ra) since VD=VR and VD=VDQ2*(Ra/(Ra+Rb)). If the bit line leakage current becomes greater than the pumping current, VDQ1 and VDQ2 will drop below the target value, making overerase correction inefficient. A bit switch 124 is selected by the column decoder to turn on the electrical path from VDQ2 to the selected bit line 104. In FIG. 2, the bit switch 124 includes pass transistors Qbs0, Qbs1, and Qbs2. There is a voltage drop across each pass transistor that further reduces the value of VBL below its target value, such that VBL equals VDQ2−(I*Req) where Req is the equivalent resistance of bit switch 124 and PMOS QPL[n] and I is the bit line current. PMOS QPLn is an I/O switch transistor associated with a plurality of bit lines for selecting a group of bit lines associated with an I/O for writing. The voltage drop across bit switch 124 increases as current in bit line 104 increases.
U.S. Pat. No. 6,046,932 to Bill et al. proposes a solution to problems associated with Cleveland et al. and described above. A resistor is connected in series between the source of the cell and ground. The leakage current raises the source voltage and forces deselected cells to have lower leakage currents by the self-generated body effect. This method is applied to programming and overerase correction. The drain to source voltage will be lower than VDQ2. In order to have efficient over erase correction or programming, VDQ2 will be set at a higher target value to sustain the drain to source voltage at high enough level. However, when the bit line leakage current is reduced, the voltage drop on the resistor is reduced, and the drain to source voltage is increased and approaches VDQ2. The variation of the drain-to-source voltage maybe as high as 1V. At this time, the drain to source voltage may become too high, which will create more hot holes that damage the Si—SiO2 interface of the memory cell. The result is the degradation of program/erase cycling reliability.
Therefore, there remains a need for a method and circuit for controlling the bit line current during overerase correction operation and for more efficiently performing overerase correction.